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Below is a cache of http://www.truecircuits.com/images/pdfs/maneatis03.pdf. It's a snapshot of the page taken as our search engine crawled the Web.
The web site itself may have changed. You can check the current page or check for previous versions at the Internet Archive. Yahoo! is not affiliated with the authors of this page or responsible for its content. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL - Solid-State Circuits, IEEE Journal of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003 1795 Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL John G. Maneatis, Member, IEEE, Jaeha Kim, Student Member, IEEE, Iain McClatchie, Jay Maxey, and Manjusha Shankaradas AbstractA self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear pro-
grammable current mirror for constant loop dynamics that scale
with reference frequency and are independent of multiplication
factor, output frequency, process, voltage, and temperature. The
PLL achieves a multiplication range of 14096 with less than 1.7%
output jitter. Fabricated in 0.13- m CMOS, the area is 0.182 mm 2 and the supply is 1.5 V. Index TermsAdaptive bandwidth, analog circuits, clock gener- ation, clock multiplication, frequency synthesis, phase-locked loop
(PLL), self-biased. I. I NTRODUCTION O NE CHALLENGE in designing phase-locked loops
(PLLs) for application-specific integrated circuits (ASICs) is providing ample flexibility for a wide variety of
applications, including processors and video/chip interfaces.
PLLs commonly are used to take low-frequency off-chip
clocks, typically from crystals, and generate high-frequency
on-chip clocks. The diversity of ASIC applications has also led
to diversity in operating frequencies and multiplication factors
required from PLLs. For each PLL output frequency and multiplication factor, the loop parameters must be adjusted to minimize jitter and to guar-
antee stability. There are two jitter parameters of interest. One
is long-term jitter, which is the deviation over time in the output
clock edge time locations from those of an ideal clock output
that is perfectly periodic. The other is period jitter, which is the
variation over time in the period of the output clock. For a clock
generator PLL, the output clock should track the input clocks as
close as possible to minimize long-term jitter. It is also impor-
tant to minimize the amount of period jitter. These objectives pose a set of requirements on the loop parameters of the PLL. The loop bandwidth, which describes
the response rate of the PLL, should be about 1/20 of the
reference frequency. The damping factor, which describes the
stability, should be about one. The third-order pole, which
helps minimize period jitter, should be set at about 1/2 of the
reference frequency. All of these loop parameters depend on Manuscript received April 15, 2003; revised June 22, 2003.
J. G. Maneatis and I. McClatchie are with True Circuits, Inc., Los Altos, CA 94022 USA (e-mail: maneatis@truecircuits.com). J. Kim was with True Circuits, Inc., Los Altos, CA 94022 USA. He is now with Seoul National University, Seoul 151-742, Korea. J. Maxey and M. Shankaradas are with Texas Instruments Incorporated, Dallas, TX 75243-0199 USA. Digital Object Identifier 10.1109/JSSC.2003.818298 specific circuit parameters, such as the charge pump current
and the loop filter resistance. Thus, these parameters must vary
with output frequency and multiplication factor. The diverse values of output frequency and multiplication factor can be addressed by designing a different PLL for each
ASIC. This strategy makes it easier to meet constrained target
specifications with less challenging circuits, but verifying all
the designs in silicon for the ASICs that a company plans to
build would be time consuming and costly. A better strategy is
to create a single PLL design that can be used for clock genera-
tion on a large set of ASICs. With only one design, verification
in silicon is much easier, but the design becomes more difficult
as loop parameters must adjust automatically to satisfy a wide
range of output frequencies and multiplication factors. Self-biased PLLs [2] can solve part of the problem by adjusting for different output frequencies. Specifically, they
achieve a fixed loop-bandwidth-to-reference-frequency ratio
and damping factor, which are largely independent of process,
voltage, and temperature. This property allows the bandwidth
to be set to a precise fraction of the reference frequency
independent of the actual reference frequency, which will
minimize long-term jitter over a wide reference frequency
range. However, self-biased PLLs do not adjust for different
multiplication factors. In particular, the bandwidth-to-refer-
ence-frequency ratio and the damping factor both vary with the
multiplication factor. Also, with an additional third-order pole,
the pole-frequency-to-reference-frequency ratio will also vary
with the multiplication factor. To handle a large multiplication
range, all of these ratios should be fixed and independent of the
multiplication factor. This paper describes a self-biased clock generator PLL ca- pable of multiplying by 1 to 4096 with near-constant period
jitter over the whole range [1]. The PLL extends the self-biased
PLL architecture with a new loop filter structure that produces
constant loop dynamics that scale with reference frequency and
are virtually independent of the multiplication factor, output fre-
quency, process, and environmental conditions. This paper begins by reviewing the fundamentals of a self-bi- ased PLL design and how it obtains tracking loop dynamics.
Pattern jitter, a form of period jitter caused by multiplication,
is discussed in Section III. Section IV presents a loop filter
architecture that solves the scaled problem while addressing pattern jitter. A number of key circuits used inside the PLL
design are described in Section V. Finally, some experimental
results demonstrating the effectiveness of the clock generator
PLL architecture in minimizing output jitter are presented in
Section VI. 0018-9200/03$17.00
The web site itself may have changed. You can check the current page or check for previous versions at the Internet Archive. Yahoo! is not affiliated with the authors of this page or responsible for its content. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL - Solid-State Circuits, IEEE Journal of IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003 1795 Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL John G. Maneatis, Member, IEEE, Jaeha Kim, Student Member, IEEE, Iain McClatchie, Jay Maxey, and Manjusha Shankaradas AbstractA self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear pro-
grammable current mirror for constant loop dynamics that scale
with reference frequency and are independent of multiplication
factor, output frequency, process, voltage, and temperature. The
PLL achieves a multiplication range of 14096 with less than 1.7%
output jitter. Fabricated in 0.13- m CMOS, the area is 0.182 mm 2 and the supply is 1.5 V. Index TermsAdaptive bandwidth, analog circuits, clock gener- ation, clock multiplication, frequency synthesis, phase-locked loop
(PLL), self-biased. I. I NTRODUCTION O NE CHALLENGE in designing phase-locked loops
(PLLs) for application-specific integrated circuits (ASICs) is providing ample flexibility for a wide variety of
applications, including processors and video/chip interfaces.
PLLs commonly are used to take low-frequency off-chip
clocks, typically from crystals, and generate high-frequency
on-chip clocks. The diversity of ASIC applications has also led
to diversity in operating frequencies and multiplication factors
required from PLLs. For each PLL output frequency and multiplication factor, the loop parameters must be adjusted to minimize jitter and to guar-
antee stability. There are two jitter parameters of interest. One
is long-term jitter, which is the deviation over time in the output
clock edge time locations from those of an ideal clock output
that is perfectly periodic. The other is period jitter, which is the
variation over time in the period of the output clock. For a clock
generator PLL, the output clock should track the input clocks as
close as possible to minimize long-term jitter. It is also impor-
tant to minimize the amount of period jitter. These objectives pose a set of requirements on the loop parameters of the PLL. The loop bandwidth, which describes
the response rate of the PLL, should be about 1/20 of the
reference frequency. The damping factor, which describes the
stability, should be about one. The third-order pole, which
helps minimize period jitter, should be set at about 1/2 of the
reference frequency. All of these loop parameters depend on Manuscript received April 15, 2003; revised June 22, 2003.
J. G. Maneatis and I. McClatchie are with True Circuits, Inc., Los Altos, CA 94022 USA (e-mail: maneatis@truecircuits.com). J. Kim was with True Circuits, Inc., Los Altos, CA 94022 USA. He is now with Seoul National University, Seoul 151-742, Korea. J. Maxey and M. Shankaradas are with Texas Instruments Incorporated, Dallas, TX 75243-0199 USA. Digital Object Identifier 10.1109/JSSC.2003.818298 specific circuit parameters, such as the charge pump current
and the loop filter resistance. Thus, these parameters must vary
with output frequency and multiplication factor. The diverse values of output frequency and multiplication factor can be addressed by designing a different PLL for each
ASIC. This strategy makes it easier to meet constrained target
specifications with less challenging circuits, but verifying all
the designs in silicon for the ASICs that a company plans to
build would be time consuming and costly. A better strategy is
to create a single PLL design that can be used for clock genera-
tion on a large set of ASICs. With only one design, verification
in silicon is much easier, but the design becomes more difficult
as loop parameters must adjust automatically to satisfy a wide
range of output frequencies and multiplication factors. Self-biased PLLs [2] can solve part of the problem by adjusting for different output frequencies. Specifically, they
achieve a fixed loop-bandwidth-to-reference-frequency ratio
and damping factor, which are largely independent of process,
voltage, and temperature. This property allows the bandwidth
to be set to a precise fraction of the reference frequency
independent of the actual reference frequency, which will
minimize long-term jitter over a wide reference frequency
range. However, self-biased PLLs do not adjust for different
multiplication factors. In particular, the bandwidth-to-refer-
ence-frequency ratio and the damping factor both vary with the
multiplication factor. Also, with an additional third-order pole,
the pole-frequency-to-reference-frequency ratio will also vary
with the multiplication factor. To handle a large multiplication
range, all of these ratios should be fixed and independent of the
multiplication factor. This paper describes a self-biased clock generator PLL ca- pable of multiplying by 1 to 4096 with near-constant period
jitter over the whole range [1]. The PLL extends the self-biased
PLL architecture with a new loop filter structure that produces
constant loop dynamics that scale with reference frequency and
are virtually independent of the multiplication factor, output fre-
quency, process, and environmental conditions. This paper begins by reviewing the fundamentals of a self-bi- ased PLL design and how it obtains tracking loop dynamics.
Pattern jitter, a form of period jitter caused by multiplication,
is discussed in Section III. Section IV presents a loop filter
architecture that solves the scaled problem while addressing pattern jitter. A number of key circuits used inside the PLL
design are described in Section V. Finally, some experimental
results demonstrating the effectiveness of the clock generator
PLL architecture in minimizing output jitter are presented in
Section VI. 0018-9200/03$17.00
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